Circuit for configuring a redundant bond pad for probing a semiconductor

ABSTRACT

An integrated device includes a redundant bond pad for accessing internal circuitry in the event that the main bond pad for that circuitry is difficult to access with testing equipment. Signals from the redundant bond pad are biased to ground during normal operations of the integrated device. In order to test the relevant internal circuitry, a voltage is applied to a Test Mode Enable bond pad, overcoming the bias that grounds the redundant bond pad. In addition, the signal from the Test Mode Enable bond pad serves to ground any transmission from the main bond pad. As a result, the redundant bond pad may be used to test the relevant internal circuitry given its accessible location in relation to the testing equipment.

RELATED APPLICATIONS

[0001] This application is a continuation of U.S. application Ser. No.09/164,195, filed on Sep. 30, 1998 and issued as U.S. Pat. No.6,107,111; which is a divisional of U.S. application Ser. No.08/760,153, filed Dec. 3, 1996, and issued as U.S. Pat. No. 5,859,442.

TECHNICAL FIELD

[0002] The present invention relates generally to electronic devicesand, more specifically, to a circuit for providing a redundant bond padfor probing semiconductor devices.

BACKGROUND OF THE INVENTION

[0003] As seen in FIG. 1, one or more dies are formed in a conventionalmanner on a wafer which, in turn, is formed from a semiconductormaterial such as silicon. Each die has an integrated circuit or devicethat has been formed but not yet detached from the wafer. Further, eachdie on the wafer can be tested by placing a set of mechanical probes inphysical contact with the die's bond pads. The bond pads provide aconnection point for testing the integrated circuitry formed on the die.The probes apply voltages to the input bond pads and measure theresulting output electrical signals on the output bond pads. Not allbond pads on a die, however, are easily accessible by these devices.Given the dies' arrangement in FIG. 1, for example, it is generallyeasier to probe the long sides of the die; the short sides of the dieare usually too close to the other dies to allow sufficient clearancefor testing purposes. Thus, it can be difficult to test circuits thatare coupled to an inaccessible bond pad.

[0004] Requiring bond pads to be located only in the areas accessibleduring testing may lead to inefficient and complex circuit layouts. Oneknown solution, as shown in FIG. 3, is to attach another bond pad, onethat can be reached by a testing device, to the same wire used by theoriginal bond pad. This solution, however, tends to increase the inputcapacitance. Attempts at minimizing this capacitance will result in theuse of more die space.

[0005] A second known solution is to multiplex (mux) two input bufferstogether, as illustrated in FIG. 4, once again allowing an testable bondpad to access circuitry. With this mux circuit, however, signals fromthe original pad take longer to reach the die's integrated circuitry. Inaddition, if input is designed to be received from multiple inputbuffers in a parallel configuration, this muxing solution would requireduplicating large portions of the input circuitry, once again taking upa great deal of die space.

SUMMARY OF THE INVENTION

[0006] The present invention provides a circuit allowing an alternateaccess point to be used in testing the integrated circuitry, wherein thecircuitry is usually accessed at another point that is difficult toreach with testing equipment. The resulting advantage of thisimplementation is that the circuit may be easily tested. As anotheradvantage, the circuit may operate during testing at the same polarityinput as used in normal operations of the die without an increase incapacitance. Moreover, the preferred embodiments of this invention maybe used to test the circuit without appreciably slowing down the time toinput signals. Further, the invention will not require the duplicationof circuitry related to the input of data. For purposes of testing inone preferred implementation, the circuit also prevents the use of aninput pad employed during normal operation. dr

BRIEF DESCRIPTION OF THE DRAWINGS

[0007]FIG. 1 is a top view of a semiconductor wafer with dies formedthereon as is known in the art.

[0008]FIG. 2 is a top view of a die of FIG. 1.

[0009]FIG. 3 is a block diagram demonstrating a solution in the priorart for testing the circuitry on a die.

[0010]FIG. 4 is a block diagram demonstrating a second such solution inthe prior art.

[0011]FIG. 5a is a schematic diagram of one exemplary embodiment inaccordance with the present invention.

[0012]FIG. 5b is an top-down view of a transistor configured forprotection against electrostatic discharge.

[0013]FIG. 5c is a schematic diagram of the exemplary embodiment of FIG.5a as used with a modified operations circuit.

[0014]FIG. 6a is a schematic diagram of a second exemplary embodiment ofthe present invention.

[0015]FIG. 6b is a more detailed schematic diagram of the exemplaryembodiment in FIG. 6a.

[0016]FIG. 7 is a schematic diagram of a third exemplary embodiment ofthe present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017]FIG. 2 illustrates the top view of a die 12 that is formed in aconventional manner on a wafer. For purposes of clarity, the wafer andadditional dies that may be formed on that wafer have been omitted fromFIG. 2. The sides of die 12 contain input bond pads 15, to whichexternal lead wires can be bonded. The bond pads 15 connect tooperations circuits 14, such as row address or decoding circuits, withinthe die 12. It is understood in the art that a die could contain manysuch bond pads 15 and operations circuits 14. Duplication of theseelements has been limited in FIG. 2 for purposes of clarity. Some bondpads 15 are more easily accessible by testing devices than are others.One element affecting accessibility is the spacing between dies 12. Forpurposes of distinguishing the accessibility of bond pads as illustratedin FIG. 1, areas where the bond pads are more easily accessible arelabeled “16,” whereas areas where bond pads are relatively inaccessibleare denoted by “18.”

[0018] Occasionally, a particular die 12 is configured so that, during anormal operations mode, an operations circuit 14 is connected to aninput bond pad 20 that is in an inaccessible area 18 concerning testingdevices. Given such- inaccessibility, it can be difficult to applysignals to the operations circuit 14 during a test mode. This isparticularly true during the probe of dies that are still part of awafer. Through the current invention, however, a probe bond pad 22 in anaccessible area 16 can be connected to the operations circuit 14 duringthe test mode, thereby allowing for easy testing.

[0019] An exemplary testing circuit 24, described below in detail andillustrated in FIG. 5a, is used to connect the probe pad 22 to theoperations circuit 14 during the test mode for that circuit. Theoperation of the testing circuit 24 is controlled by an enable signal.In the preferred embodiment, this signal is provided by the testingdevice through a Test Mode Enable bond pad 26. Thus, during the testmode, the testing device transmits the enable signal by way of the TestMode Enable bond pad 26. In response, the testing circuit 24 couples theprobe bond pad 22 to the operations circuit 14, which is normally drivenby signals applied to input bond pad 20.

[0020]FIG. 5a is a schematic diagram of one embodiment of the testingcircuit 24. The testing circuit 24 contains a first conducting path 28from the input bond pad 20 to the operations circuit 14. The firstconducting path 28 is also coupled to the drain of a first n-channeltransistor Q2, which has a source coupled to ground. This firstn-channel transistor Q2 is also configured for electrostatic discharge(ESD) protection, as illustrated in FIG. 5b. As with standardtransistors of this type, the first n-channel transistor Q2 is comprisedof a first conductive strip 50, which, in this case, leads to the firstconducting path 28 and, ultimately, to input bond pad 20. A secondconductive strip 52 leads to ground, and a gate 54 is interposed betweenthe first and second conductive strips 50 and 52. Further, there existsan n+ active area 56 between the gate 54 and the first conductive strip50. This n+ active area 56 is preferably in a vertical arrangement withsaid first conductive strip 50 and communicates with that strip 50 via aseries of contacts 58. Unlike standard transistors, this n+ active area56 is sufficiently large enough to create a relatively high active arearesistance, generally around 1 KΩ, thereby preventing ESD damage.

[0021] Returning to FIG. 5a, a second conducting path 32 connects theprobe bond pad 22 with a NOR gate 34. The second conducting path 32 isalso coupled to the drain of a second n-channel transistor Q4. A thirdconducting path 38 couples the Test Mode Enable bond pad 26 with a firstinverter 40. Between these two devices, however, the third conductingpath 38 is also coupled with the gate 54 of the first n-channeltransistor Q2 as well as a low-bleed current device, known to thoseskilled in the art as a long L device 42. The first inverter 40 has aninput coupled to the third conducting path 38 and an output coupled tothe gate of the second n-channel transistor Q4. The NOR gate 34 has afirst input 44, which receives an enabling signal for the operationscircuit 14. The NOR gate 34 also has a second input coupled to thesecond conducting path 32, and an output. Finally, the circuit containsa second inverter 46, which has an input coupled to the output of theNOR gate 34. The output of the second inverter 46 is coupled with theoperations circuit 14.

[0022] During normal use of the operations circuit 14, the Test ModeEnable bond pad 26 is not receiving an enabling signal from any testingdevice. Therefore, the long L device 42 serves to bleed to ground anyremaining low current within the third conducting path 38. The lack ofcurrent in the third conducting path 38 turns off the first n-channeltransistor Q2. With the first n-channel transistor Q2 off, the firstconducting path 28 may freely transmit signals from the input bond pad20 to the operations circuit 14. In the schematic illustrated in FIG.5a, the signal transmitted by the input bond pad 20 is an external RowAddress Strobe (XRAS*) signal. Further, operations circuit 14 is aninput buffer which accepts the industry standard input levels of thetransmitted XRAS* signal and modifies them to internal V_(CC) and groundlevels. It is known that such a circuit may have differentconfigurations. The operations circuit in FIG. 5c demonstrates analternate configuration, wherein optional transistors have been omitted,including those used for further tuning the XRAS* signal.

[0023] Returning to the third conducting path 38, the lack of current inthat path results in a logic 0 value transmitted to the first inverter40. It follows that the output of the first inverter is at logic 1,which turns on the second n-channel transistor Q4. Once activated, thesecond n-channel transistor Q4 bleeds current from the second conductingpath 32, thereby grounding any signals from probe bond pad 22.

[0024] Because the second conducting path 32 is at logic 0 during normaloperations mode, the signal reaching the operations circuit 14 from thesecond inverter 46 will match the control logic signals received by thefirst input 44 of the NOR gate 34. For example, given a logic 1 valuereceived by the first input 44 and the logic 0 of the second input, theoutput of the NOR gate will be a logic 0, which will be inverted by thesecond inverter 46 to logic 1. This logic 1 will serve as an input forthe operations circuit 14. If, on the other hand, the first input 44receives a logic 0, the two logic 0 inputs for the NOR gate 34 result ina logic 1 output, which is inverted by the second inverter to result ina logic 0 being input into the operations circuit 14.

[0025] During the test mode of the operations circuit 14, the Test ModeEnable bond pad 26 is driven with a sufficient voltage to overcome thebleeding effects of the long L device 42 and send a signal of logic 1 tothe third conducting path 38. This signal turns on the first n-channeltransistor Q2, thereby grounding any input signal that would come fromthe input bond pad 20. The logic 1 signal of the third conducting path38 also goes through the first inverter 40. The resulting logic 0 valueturns off the second n-channel transistor Q4 that had been groundingsignals from the probe bond pad 22. As a result, signals such as XRAS*that once issued from the input bond pad 20 may now be input using themore accessible probe bond pad 22. The NOR gate 34 receives both asignal enabling the operations circuit 14 as well as transmissions fromthe probe bond pad 22. The NOR gate 34 output is inverted by the secondinverter 46, and the result is entered into the operations circuit 14.

[0026] In another embodiment illustrated in FIGS. 6a and 6 b, a secondinput buffer 48 may be used with the probe bond pad 22 in order topreserve a trip point equivalent to that of other bond pads 15. In thisembodiment, the second input buffer 48 has a configuration similar tothat of the operations circuit 14 of FIG. 5c.

[0027] In a third embodiment, shown in FIG. 7, the signals that passedthrough the NOR gate 34 and the second inverter 46 in earlierembodiments are instead coupled directly into the operations circuit 14with the addition of one n-channel transistor Q6 and one p-channeltransistor Q8. This embodiment has the benefit of allowing multiplepoints of access for test signals, rather than requiring all of the testsignals to be input at only one location. This is not the most preferredembodiment, however, as the additional transistors Q6 and Q8 requireadditional die space.

[0028] One of ordinary skill in the art can appreciate that, althoughspecific embodiments of this invention have been described above forpurposes of illustration, various modifications may be made withoutdeparting from the spirit and scope of the invention. For example, thetesting circuit could be modified so that a single Test Mode Enable padcould enable a plurality of probe bond pads, while simultaneouslygrounding the corresponding input bond pads. It is also possible toconfigure the testing circuit to provide for probe bond pads formeasuring the output of an operations circuit in the event the outputbond pad is inaccessible. In addition, exemplary embodiments within thescope of the current invention are not limited to those involved withinaccessible or redundant bond pads. Rather, the current inventionincludes within its scope embodiments addressing components including,but not limited to, an access point; an input; a terminal; a pad ingeneral, including one not limited to bonding; and a contact pad.Further, exemplary embodiments within the scope of the current inventionare not limited to those involved with a long L device. Rather, thecurrent invention includes within its scope embodiments addressingcomponents and acts for electrically grounding, as well as others.Accordingly, the invention is not limited except as stated in theclaims.

What is claimed is:
 1. An integrated circuit comprising: at least onetest circuit; at least one main bond pad coupled to said test circuit;at least one probe bond pad corresponding to said main bond pad andcoupled to said test circuit; a test signal conduit coupled to said testcircuit; at least one main circuit coupled to said test circuit; whereinsaid test circuit is configured to propagate signals between said mainbond pad and said main circuit, and said test circuit is furtherconfigured to selectively propagate signals between said probe bond padand said main circuit in response to a signal carried by said testsignal conduit.
 2. The integrated circuit of claim 1, wherein said testsignal conduit is configured to carry a test vector to said testcircuit.
 3. The integrated circuit of claim 1, wherein said test signalconduit is a test-mode-enable bond pad.
 4. An integrated devicecomprising: a first bond pad in selective electrical connection with afirst conductive path; a second bond pad in selective electricalconnection with a second conductive path; and a selection circuitcoupled to said first and second conductive paths, wherein saidselection circuit operable to receive an enable signal that has a firstvalue during a first operational mode of said integrated device and asecond value during a second operational mode of said integrated device,and wherein said selection circuit is operable to couple said first bondpad to said first conductive path in response to said first value; saidselection circuit further operable to couple said second bond pad tosaid second conductive path in response to said second value.
 5. Thedevice in claim 4, wherein said selection circuit is further operable todecouple said first bond pad from said first conductive path in responseto said second value.
 6. The device in claim 5, further comprising abuffer interposed between said second bond pad and said secondconductive path.
 7. The device in claim 6, wherein said first and secondbond pads are configured to receive input signals.
 8. A semiconductorwafer comprising: a plurality of semiconductor dies, each die having afirst area and a second area, each die comprising: a first bond pad insaid first area; a second bond pad in said second area; a test signalconductive path; a circuit; and a testing device coupled to said firstbond pad, said second bond pad, said test signal conductive path, andsaid circuit, wherein said testing device is operable to allowtransmission of signals between said circuit and said first bond pad,and said testing device is further operable to establish thetransmission of signals between said circuit and said second bond padupon a test signal sent by way of said test signal conductive path.
 9. Aswitching device for an operations circuit comprising: a firstconductive path coupled to said operations circuit; a second conductivepath coupled to said operations circuit; a first bond pad coupled tosaid first conductive path; a second bond pad coupled to said secondconductive path; a selection circuit coupled to a third bond pad, saidfirst conductive path, and to said second conductive path, wherein saidselection circuit is configured to allow grounding of said secondconductive path during a first mode of operation of said operationscircuit and grounding of said first conductive path during a second modeof operation of said operations circuit.
 10. The device in claim 9,wherein said selection circuit is further configured to preventgrounding of said second conductive path during said second mode ofoperation and to prevent grounding of said first conductive path duringsaid first mode of operation.
 11. The device in claim 10, furthercomprising a control logic signal conduit coupled to said secondconductive path.
 12. The device in claim 10, further comprising acontrol logic signal conduit directly coupled to said operationscircuit.
 13. The device in claim 12, wherein said second bond pad iscoupled directly to said operations circuit.
 14. A switching assemblyfor an operations circuit, comprising: an output node coupled to saidoperations circuit; a primary input selectively coupled to said outputnode; a test input selectively coupled to said output of said assembly;and a selection mechanism electrically interposed between said inputsand said output.
 15. The switching assembly in claim 14, furthercomprising: a test-mode-enable input coupled to said selection mechanismand configured to carry a test signal to said selection mechanism,wherein said selection mechanism is configured to allow electricalcommunication between said test input and said operations circuit inresponse to said test signal.
 16. The switching assembly of claim 15,wherein said selection mechanism is further configured to preventelectrical communication between said test input and said operationscircuit in the absence of said test signal.
 17. A testing circuit for anoperations circuit comprising: a main output terminal coupled to a maininput terminal; a first electrically grounding device interposed betweensaid main output terminal and said main input terminal; a test outputterminal coupled to a test input terminal; a second electricallygrounding device interposed between said test output terminal and saidtest input terminal; and a test-mode-enable input terminal coupled tosaid first and second electrically grounding devices, wherein saidtest-mode-enable input terminal is configured to selectively drive saidelectrically grounding devices.
 18. The testing circuit of claim 17,wherein: said first electrically grounding device is a first n-channeltransistor having a first gate, wherein said first electricallygrounding device is configured for ESD protection; and said secondelectrically grounding device is a second n-channel transistor having asecond gate.
 19. The testing circuit of claim 18, further comprising: aninverter having an inverter output coupled to said second gate and aninverter input coupled to said test-mode-enable input terminal; and aconducting path interposed between said inverter input and saidtest-mode-enable input terminal, wherein said conducting path isconnected to said first gate.
 20. The testing circuit of claim 19,further comprising: a third electrically grounding device interposedbetween said test-mode-enable input terminal and said conducting path,wherein said third electrically grounding device is biased to generallyprevent the transmission of signals from said test-mode-enable inputterminal.
 21. The testing circuit of claim 20, wherein said thirdelectrically grounding device is a long L device.
 22. A testingapparatus for an operations circuit coupled to a primary pad, saidtesting apparatus comprising: a mode-enable path coupled to saidoperations circuit, wherein said mode-enable path has a trip point andis configured to transmit a forcing voltage; and a redundant pad coupledto said mode-enable path and to said operations circuit, wherein saidredundant pad is configured to emulate said primary pad in response to atransmission of said forcing voltage through said mode-enable path. 23.The testing apparatus of claim 22, wherein said operations circuit hasan enabling function, and said redundant pad is configured to controlsaid enabling function in response to said transmission of said forcingvoltage.
 24. The testing apparatus in claim 23, further comprising amode-enable pad coupled to said mode-enable path, wherein saidmode-enable pad is configured to receive said forcing voltage.
 25. Thetesting apparatus in claim 24, wherein said operations circuit is aninput buffer.
 26. A method for configuring bond pad connections in anintegrated circuit comprising: coupling a first bond pad to a firstconductive path while said integrated circuit is in a first operationalmode; and coupling a second bond pad to a second conductive path whilesaid integrated circuit is in a second operational mode.
 27. The methodin claim 26, further comprising decoupling said first bond pad from saidfirst conductive path while said integrated circuit is in said secondoperational mode.
 28. The method in claim 27, further comprisingreceiving a signal for changing between said first operational mode andsaid second operational mode.
 29. The method in claim 28, wherein saiddecoupling step comprises holding said first conductive path at asubstantially constant potential while said integrated circuit is insaid second operational mode.
 30. The method in claim 29, wherein saiddecoupling step comprises grounding said first conductive path.
 31. Themethod in claim 30, further comprising temporarily storing datatransmitted between said second conductive path and said second bondpad.
 32. A method for testing an integrated circuit using generally thesame polarity as in non-test operations of said integrated circuit,wherein said method comprises: providing a first contact pad; providinga second contact pad; providing a communication between said firstcontact pad and said integrated circuit during a non-test mode; andswitching to a communication between said second contact pad and saidintegrated circuit during a test mode.
 33. The method in claim 32,wherein the step of providing a communication comprises: controlling atleast one enabling function of said integrated circuit by sendingsignals through said first contact pad.
 34. The method in claim 33,wherein the switching step comprises controlling said enabling functionof said integrated circuit by sending signals through said secondcontact pad.
 35. The method of claim 34, wherein said second contact padfunctions during said test mode in a manner generally similar to that ofsaid first contact pad during said non-test mode.
 36. A method forproviding alternate accesses to an integrated circuit coupled to a firstcontact pad, comprising: coupling a second contact pad to saidintegrated circuit; initiating a test mode for said integrated circuit;preventing transmission of signals from said first contact pad; andenabling transmission of signals from said second contact pad.
 37. Themethod in claim 36, wherein said step of initiating a test mode for saidintegrated circuit further comprises accessing a test vector.
 38. Themethod in claim 37, wherein said step of accessing a test vectorcomprises: applying a first test signal to a first node interposedbetween said first contact pad and said integrated circuit; and applyinga second test signal to a second node interposed between said secondcontact pad and said integrated circuit.
 39. A method for preparing adie on a wafer for testing, comprising: providing a first conductivepath coupled to a first pad and to an operations circuit; providing asecond conductive path coupled to a second pad and to said operationscircuit; providing a third conductive path coupled to a third pad and tosaid first conductive path and to said second conductive path; groundingsaid second conductive path and said third conductive path during afirst operational mode; maintaining electrical communication betweensaid first pad and said operations circuit during said first operationalmode; grounding said first conductive path during a second operationalmode; and enabling electrical communication between said second pad andsaid operations circuit during said second operational mode.
 40. Themethod of claim 39, wherein said step of grounding said secondconductive path and said third conductive path further comprises:generally biasing said third conductive path to ground; and providingelectrical grounding communication between said third conductive pathand said second conductive path.
 41. The method of claim 40, wherein:said step of generally biasing said third conductive path to groundcomprises coupling a third-path electrical grounding device to saidthird conductive path; and said step of providing electrical groundingcommunication comprises: coupling a second-path electrical groundingdevice to said second conductive path, and driving said second-pathelectrical grounding device from said third conductive path.
 42. Themethod of claim 41, wherein said step of enabling electricalcommunication between said second pad and said operations circuitcomprises: overcoming said third-path electrical grounding device; andhalting a drive communication between said third conductive path andsaid second-path electrical grounding device.
 43. The method of claim42, wherein said step of grounding said first conductive path comprises:coupling a first-path electrical grounding device to said firstconductive path; providing electrical grounding communication betweensaid third conductive path and said first conductive path; and drivingsaid first-path electrical grounding device from said third conductivepath.
 44. The method of claim 43 further comprising the step ofprotecting said first-path electrical grounding device from ESD.
 45. Amethod for generally maintaining capacitance of an integrated circuitduring testing, wherein said method comprises: configuring a primaryinput to said integrated circuit; configuring a test input to saidintegrated circuit; and enabling a switching assembly to selectivelycouple said integrated circuit to said primary input and said testinput.
 46. The method in claim 45, further comprising: providing apathway for a control logic signal to said integrated circuit; andgenerally maintaining said control logic signal to said integratedcircuit during said test and non-test modes.
 47. The method in claim 46,further comprising coupling said pathway and said test input directly tosaid integrated circuit.
 48. A method of generally maintaining inputsignal timing during testing of an integrated circuit, wherein saidmethod comprises: providing a test-mode path to a redundant pad;establishing an activation trip point for said test-mode path; forcingsaid test-mode path active; enabling a redundant pad; and controllingsaid integrated circuit through said redundant pad.
 49. The method inclaim 48, wherein said forcing step further comprises: providing atest-mode pad for said test-mode path; and applying voltage to saidtest-mode pad, wherein said voltage is at least as high as said trippoint.
 50. The method of claim 49, further comprising a step ofproviding a grounding bias that is capable of diverting signals fromsaid redundant pad to said integrated circuit.
 51. The method of claim50, wherein said enabling step comprises overcoming said grounding bias.52. The method of claim 51, wherein said removing step comprisesproviding electrical communication between said test-mode path and saidgrounding bias.